“More is different.”
P. W. Anderson · Science, 1972
BITS Pilani, K. K. Birla Goa Campus · EEE (Hons.) · Physics minor
Undergraduate electronics and electrical engineering student building toward research in memory-centric AI hardware: the physics of memory devices, the mixed-signal circuits that read and write them, and the architectures that decide how data moves.
01 · About
I am a third-year B.E. (Hons.) Electronics and Electrical Engineering student at BITS Pilani, K. K. Birla Goa Campus, with a minor in Physics.
Most of my coursework and project work sits where electronics meets physics: semiconductor devices, analog circuits, signals, and quantum mechanics. Outside the curriculum I am a research intern at CircuitEvolve, building the LLM-guided evolutionary optimizer at the core of its analog design-automation flow and leading a research section on yield-informed circuit reasoning. At BITSilicon I lead a 12-member team designing an RV32I five-stage pipelined RISC-V processor for a tape-out competition.
I am preparing for research internships in semiconductors and AI hardware and, longer term, graduate research in memory-centric AI hardware: emerging memory devices, the mixed-signal circuits that read and write them, and the architectures they serve. The premise is that data movement, not arithmetic, is becoming the binding constraint on AI systems, and that the layers deciding it run from condensed matter physics up through computer architecture. This site documents the projects, notes, and reading that connect those layers.
02 · Research direction
Everything on this page sits on one of three layers. The thread through them: in AI systems, moving data now costs more than computing with it, and the fix spans all three.
How electrons behave in solids (band structure, transport, tunneling, defects) and how that physics becomes working devices: transistor electrostatics and scaling, and the switching mechanisms of charge, ions, dipoles, and spins that emerging memories are built from.
How devices compose into amplifiers, comparators, and the periphery every memory lives or dies by: sense amplifiers, references, and write paths, with specs verified by testbenches and scoreboards, not by staring at waveforms.
Where the data actually moves: pipelines, caches, memory hierarchies, and the accelerator workloads that stress them. Machine learning enters as an instrument for the layers below (optimizers and surrogates for design), not as the destination.
The formal spine is still the Physics minor: Quantum Mechanics and Semiconductor Devices so far, statistical mechanics and solid state ahead. The long-term aim is graduate research in memory-centric AI hardware: physics-aware memory devices and the mixed-signal and architectural systems built on them. The physics is not a detour: memory devices are applied condensed matter, and the goal is to be able to follow a bit from switching mechanism to sense amplifier to workload.
03 · Vision
A working map for the next several years. One sentence holds it together:
Data movement, not arithmetic, is the bottleneck in AI computing. Work on the devices, circuits, and architectures that reduce it.
Resistive, ferroelectric, phase-change, and magnetic memories each turn a piece of condensed matter physics (ion motion, polarization, phase transitions, spin) into a stored bit. I want to work on that translation: switching mechanism to device model to array behavior, with variability and reliability kept honest. My entry points are the device-physics coursework and the Sentaurus TCAD work below.
A memory array is only as good as its periphery: sense amplifiers, comparators, data converters, write drivers. Analog compute-in-memory sharpens the same problem, since the periphery sets the accuracy and energy budget. This is where the analog training pays off, and these blocks are the natural next targets for CircuitEvolve’s SPICE-verified optimization loop.
LLM-guided evolutionary search, surrogate models, and optimization loops that treat the simulator as ground truth. CircuitEvolve is the working artifact; the direction is design automation that knows about process variation, mismatch, and yield rather than just nominal specs. It is the niche where an EE background is an advantage rather than a tax.
Why the layers below matter: accelerator workloads are increasingly bound by memory bandwidth and capacity, not FLOPs. The SAiDL study measured that at the workload level (attention’s VRAM and throughput at long context); the RISC-V processor’s roadmap of caches, memory hierarchy, and performance counters is my on-ramp to studying data movement at the architecture level.
These are directions, not achievements. The projects below are first steps; the reading log tracks the gap honestly.
04 · Featured projects
The work I would want a research mentor to look at first. Each card states what was actually done, what was learned, and what is still missing.
The LLM-guided evolutionary optimizer at the core of CircuitEvolve’s analog design-automation flow, built during a research internship there: parallel subagents propose, mutate, and critique candidate designs, a fitness pipeline scores them against extracted specifications, and every survivor is verified in SPICE across PVT corners and Monte Carlo mismatch before entering the next generation. It builds on earlier groundwork assembling simulation-ready analog datasets, testbenches, and specification extraction.
Why it matters
Automated analog sizing needs two things at once: a search that optimizes against real specifications, and data that carries enough context to define them. Raw netlists are not enough; a useful analog representation has to encode testbenches, bias conditions, specifications, and the design intent behind them, or the circuit’s meaning is lost. And the blocks where variability-aware automated sizing would matter most (sense amplifiers, comparators, data converters, the periphery of memory and compute-in-memory systems) are exactly the ones that live or die by mismatch and yield, which is what the yield-informed search is for.
What I did
What I learned
Analog data needs far more context than digital: the same netlist means different things under different bias, load, and measurement definitions. Reproducing published circuits is interpretation, not copying. And turning a specification into a single score is itself a design choice: how that curve is shaped decides what the search actually pursues.
Limitations
Papers often omit bias voltages, device models, or simulation conditions; without the original PDK, generic models reproduce qualitative behavior rather than exact published numbers. On the optimizer side, Monte Carlo sampling noise limits how finely two close candidates can be separated, and process spread is approximated by discrete corners rather than continuous variation.
candidate sizing → SPICE response → measured specs · gain line redraws on hover
A fully synthesizable 32-bit RISC-V processor in Verilog: a five-stage in-order pipeline with full forwarding, stall insertion, static branch prediction, and Harvard memory interfaces, synthesized for a Xilinx Artix-7 FPGA. I lead the 12-member team, owning microarchitecture decisions, task allocation, and integration across the RTL, verification, and synthesis workstreams. The design is being submitted to a tape-out competition with a path to silicon fabrication.
Why it matters
A pipeline is where data movement first becomes visible: hazards, stalls, and memory interfaces are the small-scale version of the bandwidth walls that dominate AI accelerators. The roadmap points the same core at that question directly, with caches, a memory hierarchy, and performance counters for studying data-movement bottlenecks in compute-intensive workloads.
What I did
Limitations
In progress: RTL and verification are under active development, and the cache / memory-hierarchy / performance-counter roadmap is stated intent, not implemented yet. Nothing here is silicon-proven until the tape-out actually happens.
RV32I · 5-STAGE · FWD · BP
five pipeline stages · one instruction issued per cycle · forwarding path draws on hover
Designed an nMOS capacitor and a 1 µm gate-length MOSFET (ND = 1020 cm−3 source/drain) in Sentaurus TCAD, then studied what changes, and what breaks, as the gate scales from 1 µm down to 20 nm.
What I did
What I learned
TCAD ties geometry and doping directly to electrical behavior: short-channel effects and DIBL stop being formulas and become visible in the band diagram.
VTH · SS · ION/IOFF · DIBL
nMOS cross-section · channel forms and the I–V curve redraws on hover; Lg marker shrinks
Two-track study for the SAiDL (Society for AI and Deep Learning, BITS Goa) summer induction: a modular decoder-only Transformer language model with swappable attention, positional encodings, and block structure on WikiText-2, plus parameter-efficient fine-tuning of DeBERTa-v3 on GLUE CoLA, all trained on a single RTX 4060.
What I did
What came out
At context 4096, linear attention cut peak VRAM from 10.6 GB to 4.7 GB and lifted throughput from ~0.8k to ~17.5k tokens/s (sparse-block reached ~33.9k). RoPE had the best perplexity at 512; ALiBi extrapolated flattest. On CoLA, LoRA, AdaLoRA, and proximal SoRA finished within seed-to-seed variance of each other.
Limitations
Diagnostic rather than fully converged: short hardware sweeps, single-seed CoLA runs, and from-scratch xLSTM/Mamba training that is not comparable to pretrained fine-tuning.
What this shows
At long context, attention is a memory problem before it is a compute problem: what the benchmarks actually measured was VRAM and bandwidth pressure, not FLOPs. This is the workload-level end of the data-movement question the rest of this page approaches from devices and circuits.
PPL · VRAM · MCC · PROX-ℓ1
attention mask · measured VRAM (GB) at ctx 4096 · loss redraws on hover
Parameterized synchronous FIFO in Verilog (configurable DATA_WIDTH and DEPTH), verified against an independent golden reference model with a per-cycle scoreboard, directed corner-case tests, and manual coverage counters.
What I did
What this shows
Verification discipline: the testbench is designed, not improvised. Bugs are caught by the scoreboard, not by staring at waveforms.
DUT · GOLDEN · SCOREBOARD · COVERAGE
Synchronous stopwatch controller in Verilog, with modular seconds (0–59) and minutes (0–99) counters under an IDLE / RUNNING / PAUSED control FSM, driven and validated from a cycle-accurate C++ program via Verilator.
What I did
What this shows
Clean synchronous RTL style, and that hardware can be driven and inspected from software in a cycle-accurate way.
IDLE → RUNNING → PAUSED · MM:SS
05 · Curriculum-based projects
Course projects from Sem-4 (2025–26). Smaller in scope than the featured work, but they are where the foundations (device behavior, signal processing, quantum mechanics, low-level systems) were actually built.
Compared Schottky and PN-junction diodes in half- and full-wave rectifiers using LTspice and bench measurements: forward drop, reverse recovery, and rectification efficiency. Schottky diodes won on low-voltage, high-frequency switching; PN diodes held up better under reverse bias.
VF · TRR · EFFICIENCY
LMS-based adaptive noise cancellation built with the DSP System Toolbox and tested on synthetic and audio signals. Studied how step size and filter order trade off convergence speed, stability, and steady-state MSE, and validated the SNR improvement.
LMS · MSE · SNR
Derived Landau quantization for a 2D electron gas in a perpendicular magnetic field and connected level degeneracy to integer quantum Hall conductance plateaus, high-mobility 2DEG systems, and metrological resistance standards.
ħωC · FILLING FACTOR ν · σXY
An interactive Whack-a-Mole game on the 8086 in MASM assembly: 8255 PPI for LED and push-button I/O, the 8253 programmable timer for randomized events, and interrupt-driven timing and scoring, simulated in Proteus.
8255 · 8253 · INT · LED/KEY
06 · Tools & skills
The languages and tools I have picked up over the last two years, from SPICE decks and TCAD to PyTorch training runs. Logos shown where an open one exists.
07 · Reading log
Books and papers, by area. Statuses are honest: “implemented” means implemented; everything else is in progress, revisiting, or queued.
The new center of gravity: device physics of RRAM, PCM, FeFET, and MRAM, compute-in-memory, and the memory-systems view of AI accelerators. Queue being assembled from review articles before committing to one device class.
queue being assembledAnalog synthesis, optimization, LLM-based EDA.
queue being assembled08 · Grad school journey
I am using my undergraduate years to build the layers that memory-centric AI hardware needs: device physics, analog and digital circuits, computer architecture, and the condensed matter physics beneath them. The other habit under construction is documenting technical work properly.
First-year groundwork: EEE core, programming, digital systems.
Device physics and the TCAD simulation lab, analog circuits, signal processing, and control. Quantum Mechanics I and Physics of Semiconductor Devices anchored the physics minor. RTL design and verification work (the FIFO and stopwatch projects) with BITSilicon; the curriculum projects above come from this period.
The SAiDL summer assignment added a working deep-learning toolset (Transformers, attention variants, parameter-efficient fine-tuning) and a first workload-level look at memory bottlenecks. The main lines of work now: a research internship at CircuitEvolve, building the LLM-guided evolutionary optimizer and leading its yield-informed extension, and leading the BITSilicon RV32I processor team toward a tape-out competition. The direction ahead has narrowed to memory-centric AI hardware; summer 2027 internship preparation and a reading queue in emerging memory devices are the current groundwork.
I am early in this. The plan for the remaining undergraduate years is to build depth rather than breadth for its own sake, document the work honestly, limitations included, and produce at least one piece of work that holds up to research scrutiny.
Selected from the full transcript, grouped by how it feeds the research direction.
09 · CV
A one-page CV is available as a PDF. The project cards above carry more detail than the CV format allows; if you are evaluating my work, they are the better starting point.
10 · Contact
I am open to research conversations, technical collaboration, and feedback on my work. Email is the fastest way to reach me.